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d a t a sh eet product speci?cation file under integrated circuits, ic02 december 1992 integrated circuits TDA9141 pal/ntsc/secam decoder/sync processor
december 1992 2 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 features multistandard pal, ntsc and secam i 2 c-bus controlled i 2 c-bus addresses can be selected by hardware alignment free few external components designed for use with baseband delay lines integrated video filters cvbs or yc input with automatic detection cvbs output vertical divider system two-level sandcastle signal v a synchronization pulse (3-state) h a synchronization pulse or clamping pulse clp input/output line-locked clock output or stand-alone i 2 c-bus output port stand-alone i 2 c-bus input/output port colour matrix and fast yuv switch comb filter enable input/output with subcarrier frequency. general description the TDA9141 is an i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor. the TDA9141 has been designed for use with baseband chrominance delay lines, and has a combined subcarrier frequency/comb filter enable signal for communication with a pal comb filter. the ic can process cvbs signals and y/c input signals. the input signal is available on an output pin, in the event of a y/c signal, it is added into a cvbs signal. the sync processor provides a two-level sandcastle, a horizontal pulse (clp or h a pulse, bus selectable) and a vertical (v a ) pulse. when the h a pulse is selected a line-locked clock (llc) signal is available at the output port pin. a fast switch can select either the internal y signal with the uv input signals, or yuv signals made of the rgb input signals. the rgb input signals can be clamped with either the internal or an external clamping signal (search tuning mode). two pins with an input/output port and an output port of the i 2 c-bus are available. the i 2 c-bus address of the TDA9141 is hardware programmable. ordering information note 1. sot232-1; 1996 december 4. extended type number package pins pin position material code TDA9141 32 sdil plastic sot232 (1)
december 1992 3 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 fig.1 block diagram.
december 1992 4 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 quick reference data symbol parameter conditions min. typ. max. unit v cc positive supply voltage 7.2 8.0 8.8 v i cc supply current - 45 - ma v 26(p-p) cvbs input voltage (peak-to-peak value) top sync - white - 1.0 - v v 26(p-p) luminance input voltage (peak-to-peak value) top sync - white - 1.0 - v v 22(p-p) chrominance burst input voltage (peak-to-peak value) - 0.3 - v v 12 luminance black-white output voltage - 1.0 - v v 14(p-p) u output voltage (peak-to-peak value) standard colour bar - 1.33 - v v 13(p-p) v output voltage (peak-to-peak value) standard colour bar - 1.05 - v v 10 sandcastle blanking voltage level - 2.5 - v v 10 sandcastle clamping voltage level - 4.5 - v v 11 v a output voltage - 5.0 - v v 17 h a output voltage - 5.0 - v v 16(p-p) llc output voltage amplitude (peak-to-peak value) - 500 - mv v 21,20 19(p-p) rgb input voltage (peak-to-peak value) 0 to 100% saturation - 0.7 - v v clamp i/o clamping pulse input/output voltage - 5.0 - v v sub subcarrier output voltage amplitude (peak-to-peak value) - 200 - mv v 15,16 o port output voltage - 5.0 - v
december 1992 5 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 fig.2 pin configuration. pinning symbol pin description - (r - y) 1 chrominance output - (b - y) 2 chrominance output u in 3 chrominance u input v in 4 chrominance voltage input scl 5 serial clock input sda 6 serial data input/output v cc 7 positive supply input dec 8 digital supply decoupling dgnd 9 digital ground sc 10 sandcastle output v a 11 vertical acquisition synchronization pulse y out 12 luminance output v out 13 chrominance v output u out 14 chrominance u output i/o port 15 input/output port o port/llc 16 output port/line-locked clock output clp/ha 17 clamping pulse/h a synchronization pulse input/output f 18 fast switch select input b 19 blue input g 20 green input r 21 red input addr (cvbs) 22 i 2 c-bus address input (cvbs output) fscomb 23 comb ?lter status input/output hpll 24 horizontal pll ?lter c 25 chrominance input y/cvbs 26 luminance/cvbs input agnd 27 analog ground filt ref 28 ?lter reference decoupling cpll 29 colour pll ?lter xtal 30 reference crystal input xtal2 31 second crystal input sec ref 32 secam reference decoupling
december 1992 6 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 functional description general the TDA9141 is an i 2 c-bus controlled, alignment-free pal/ntsc/secam colour decoder/sync processor which has been designed for use with baseband chrominance delay lines. in the standard operating mode the i 2 c-bus address is 8a. if the address input is connected to the positive rail the address will change to 8e. input switch warning: t he voltage on the chrominance pin must never exceed 5.5 v. i f it does the ic enters a test mode . the TDA9141 has a two pin input for cvbs or yc signals which can be selected via the i 2 c-bus. the input selector also has a position in which it automatically detects whether a cvbs or yc signal is on the input. in this input selector position, standard identification first takes place on an added y/cvbs and c input signal. after that, both chrominance signal input amplitudes are checked once and the input with the strongest chrominance burst signal is selected. the input switch status is read out by the i 2 c-bus via output bit yc. cvbs output in the standard operating mode with the i 2 c-bus address 8a, a cvbs output signal is available on the address pin, which represents either the cvbs input signal or the y/c input signal, added into a cvbs signal rgb colour matrix warning: t he voltage on the u in pin must never exceed 5.5 v. i fit does the ic enters a test mode . the TDA9141 has a colour matrix to convert rgb input signals into yuv signals. a fast switch, controlled by the signal on pin f and enabled by the i 2 c-bus via efs (enable fast switch), can select between these yuv signals and the yuv signals of the decoder. the y signal is internally connected to the switch. the - (r - y) and - (b - y) output signals of the decoder have to first be delayed in external baseband chrominance delay lines. the outputs of the delay lines must be connected to the uv input pins. if the rgb signals are not synchronous with the selected decoder input signal, clamping of the rgb input signals is possible by i 2 c-bus selection of stm (search tuning mode), efs and by feeding an external clamping signal to the clp pin. also in search tuning mode the va output will be in a high impedance off-state. standard identi?cation the standards which the TDA9141 can decode are dependent on the choice of external crystals. if a 4.4 mhz and a 3.6 mhz crystal are used then secam, pal 4.4/3.6 and ntsc 4.4/3.6 can be decoded. if two 3.6 mhz crystals are used then only pal 3.6 and ntsc 3.6 can be decoded. which 3.6 mhz standards can be decoded is dependent on the exact frequencies of the 3.6 mhz crystals. in an application where not all standards are required only one crystal is sufficient (in this instance the crystal must be connected to the reference crystal input (pin 30)). if a 4.4 mhz crystal is used it must always be connected to pin 30. both crystals are used to provide a reference for the filters and the horizontal pll, however, only the reference crystal is used to provide a reference for the secam demodulator. to enable the calibrating circuits to be adjusted exactly two bits from i 2 c-bus subaddress 00 are used to indicate which crystals are connected to the ic. the standard identification circuit is a digital circuit without external components; the search loop is illustrated in fig.3. the decoder (via the i 2 c-bus) can be forced to decode either secam or pal/ntsc (but not pal or ntsc). crystal selection can also be forced. information concerning which standard and which crystal have been selected and whether the colour killer is on or off is provided by the read out. using the forced-mode does not affect the search loop, it does, however, prevent the decoder from reaching or staying in an unwanted state. the identification circuit skips impossible standards (e.g. secam when no 4.4 mhz crystal is fitted) and illegal standards (e.g. is forced mode). to reduce the risk of wrong identification pal has priority over secam (only line identification is used for secam). integrated ?lters all filters, including the luminance delay line, are an integral part of the ic. the filters are gyrator-capacitor type filters. the resonant frequency of the filters is controlled by a circuit that uses the active crystal to tune the secam cloche filter during the vertical flyback time. the remaining filters and the luminance delay line are matched to this filter. the filters can be switched to either 4.43 mhz, 4.28 mhz or 3.58 mhz irrespective of the frequency of the active crystal. the switching is controlled by the identification circuit. in yc mode the chrominance notch filter is bypassed, to preserve full signal bandwidth. for a cvbs signal the chrominance notch filter can be bypassed by i 2 c-bus selection of tb (trap bypass). the luminance delay line delivers the y signal to the output 60 ns after the - (r - y) and - (b - y) signals have arrived at their outputs.
december 1992 7 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 this compensates for the delay of the external chrominance delay lines. colour decoder the pal/ntsc demodulator employs an oscillator that can operate with either crystal (3.6 or 4.4 mhz). if the i 2 c-bus indicates that only one crystal is connected it will always connect to the crystal on the reference crystal input (pin 30). the hue signal, which is adjustable via the i 2 c-bus, is gated during the burst for ntsc signals. the secam demodulator is an auto-calibrating pll demodulator which has two references. the reference crystal, to force the pll to the desired free-running frequency and the bandgap reference, to obtain the correct absolute value of the output signal. the vco of the pll is calibrated during each vertical blanking period, when the ic is in search mode or secam mode. if the reference crystal is not 4.4 mhz the decoder will not produce the correct secam signals. the frequency of the active crystal is fed to the fscomb output, which can be connected to an external comb filter ic. the dc value on this pin contains the comb enable information. comb enable is true when bus bit ecmb is high. if ecmb is low, the subcarrier frequency is suppressed. the external comb filter can force the dc value of fscomb low, as pin fscomb also acts as input pin. in this event the subcarrier frequency is still present. if the dc value of fscomb is high, the input switch is always forced in y/c mode, indicated by bus bit yc. sync processor ( j 1 loop) the main part of the sync circuit is a 432 f h (6.75 mhz) oscillator the frequency of which is divided by 432 to lock the phase 1 loop to the incoming signal. the time constant of the loop can be forced by the i 2 c-bus (fast or slow). if required the ic can select the time constant, depending on the noise content of the input signal and whether the loop is phase-locked or not (medium or slow). the free-running frequency of the oscillator is determined by a digital control circuit that is locked to the active crystal. when a power-on-reset pulse is detected the frequency of the oscillator is switched to a frequency greater than 6.75 mhz to protect the horizontal output transistor. the oscillator frequency is reset to 6.75 mhz when the crystal indication bits have been loaded into the ic. to ensure that this procedure does not fail it is absolutely necessary to send subaddress 00 before subaddress 01. subaddress 00 contains the crystal indication bits and when subaddress 01 is received the line oscillator calibration will be initiated (for the start-up procedure after power-on reset detection see the i 2 c-bus protocol. the calibration is terminated when the oscillator frequency reaches 6.75 mhz. the oscillator is again calibrated when an out-of-lock condition with the input signal is detected by the coincidence detector. again the calibration will be terminated when the oscillator frequency reaches 6.75 mhz. the phase 1 loop can be opened using the i 2 c-bus. this is to facilitate on screen display (osd) information. if there is no input signal or a very noisy input signal the phase 1 loop can be opened to provide a stable line frequency and thus a stable picture. the sync part also delivers a two-level sandcastle signal, which provides a combined horizontal and vertical blanking signal and a clamping pulse for the display section of the tv. vertical divider system the vertical divider system has a fully integrated vertical sync separator. the divider can accommodate both 50 and 60 hz systems; it can either locate the field frequency automatically or it can be forced to the desired system via the i 2 c-bus. a block diagram of the vertical divider system is illustrated in fig.4. the divider system operates at twice the horizontal line frequency. the line counter receives enable pulses at this line frequency, thereby counting two pulses per line. a state diagram of the controller is illustrated in fig.5. because it is symmetrical only the right hand part will be described. depending on the previously found field frequency, the controller will be in one of the count states. when the line counter has counted 488 pulses (i.e. 244 lines of the video input signal) the controller will move to the next state depending on the output of the norm counter. this can be either norm, near_norm or no_norm depending on the position of the vertical sync pulse in the previous fields. when the controller is in the norm state it generates the vertical sync pulse (vsp) automatically and then, when the line counter is at lc = 626, moves to the wait state. in this condition it waits for the next pulse of the double line frequency signal and then moves to the count state of the current field frequency. when the controller returns to the count state the line counter will be reset half a line after the start of the vertical sync pulse of the video input signal.
december 1992 8 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 when the controller is in the near_norm state it will move to the count state if it detects the vertical sync pulse within the near_norm window (i.e. 622 < lc < 628). if no vertical sync pulse is detected, the controller will move back to the count state when the line counter reaches lc = 628. the line counter will then be reset. when the controller is in the no_norm state it will move to the count state when it detects a vertical sync pulse and reset the line counter. if a vertical sync pulse is not detected before lc = 722 (if the phase 1 loop is locked in forced mode) it will move to the count state and reset the line counter. if the phase 1 loop is not locked the controller will move back to the count state when lc = 628. the forced mode option keeps the controller in either the left-hand side (60 hz) or the right-hand side (50 hz) of the state diagram. figure 6 illustrates the state diagram of the norm counter which is an up/down counter that counts up if it finds a vertical sync pulse within the selected window. in the near_norm and norm states the first correct vertical sync pulse after one or more incorrect vertical sync pulses is processed as an incorrect pulse. this procedure prevents the system from staying in the near_norm or norm state if the vertical sync pulse is correct in the first field and incorrect in the second field. if no vertical sync pulse is found in the selected window this will always result in a down pulse for the norm counter. output port and input/output port two stand-alone ports are available for external use. these ports are i 2 c-bus controlled, the output port by bus bit opb and the input/output port by bus bit opa. bus bit opa is an open-drain output, to enable input port functioning. the pin status is read out by bus via output bit ip. sandcastle figure 7 illustrates the timing of the acquisition sandcastle (asc) and the v a pulse with respect to the input signal. the sandcastle signal is in accordance with the 2-level 5 v sandcastle format. an external vertical guard current can overrule the sink current to enable blanking purposes.
december 1992 9 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 fig.3 search loop of the identification circuit. fig.4 block diagram of the vertical divider system.
december 1992 10 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 fig.5 state diagram of the vertical divider system. fig.6 state diagram of the norm counter.
december 1992 11 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 fig.7 acquisition sandcastle signal and v a pulse timing diagram.
december 1992 12 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 table 1 slave address (8a). table 2 inputs. table 3 outputs. i 2 c-bus protocol if the address input is connected to the positive supply the address will change from 8a to 8e. valid subaddresses = 00 to 0f auto-increment mode available for subaddresses. start-up procedure: read the status byte until por = 0; send subaddress 00 with the crystal indicator bits (xa and xb) indicating that only one crystal is connected to the ic; wait for 250 ms; send subaddress 01; wait for at least 100 ms; set xa, xb to the actual crystal configuration. each time before the data in the ic is refreshed, the status byte must be read. if por = 1, then the above procedure must be carried out to restart the ic. failure to stick to the above procedure may result in an incorrect line frequency after power-up or a power-dip. a6 a5 a4 a3 a2 a1 a0 r/ w 10001x1x subaddress msb lsb 00 ina inb tb ecmb foa fob xa xb 01 forf fors opa opb poc fm saf frqf 02 efs stm hu5 hu4 hu3 hu2 hu1 hu0 03 lca ------- address por fsi yc sl ip sak sbk frq
december 1992 13 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 input signals table 4 source select. ina inb source 0 0 cvbs 01yc 1 - auto cvbs/yc table 5 trap bypass. tb condition 0 trap not bypassed 1 trap bypassed table 6 comb ?lter enable. ecmb condition 0 comb ?lter disabled 1 comb ?lter enabled table 7 phase 1 time constant. foa fob mode 0 0 auto 0 1 slow 1 - fast table 8 crystal indication. xa xb crystal 0 0 2 x 3.6 mhz 0 1 1 x 3.6 mhz 1 0 1 x 4.4 mhz 1 1 3.6 and 4.4 mhz table 9 forced ?eld frequency. forf fors field frequency 0 0 auto; 60 hz if no lock 0 1 60 hz 1 0 50 hz 1 1 auto; 50 hz if no lock table 10 output value i/o port. opa condition 0 low 1 high table 11 output value o port. opb condition 0 low 1 high table 12 phase 1 loop control. poc condition 0 phase one loop closed 1 phase one loop open table 13 forced standard. note to table 13 1. if xa and xb indicate that only one crystal is connected to the ic and fm and frqf force it to use the second crystal the colour will be switched off. fm saf frqf standard 0 -- auto search 1 0 0 pal/ntsc second crystal 1 0 1 pal/ntsc reference crystal 1 1 0 illegal 1 1 1 secam reference crystal
december 1992 14 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 table 14 fast switch enable. efs condition 0 fast switch disabled 1 fast switch enabled table 15 search tuning mode. stm condition 0 search tuning mode off 1 search tuning mode on table 16 hue. function address digital number hue hu5 to hu0 000000 = - 45 111111 = +45 table 17 line-locked clock active. lca condition 0 opb/clp mode 1 llc/ha mode output signals table 18 power-on reset. por condition 0 normal mode 1 power-down mode table 19 field frequency indication. fsi condition 0 50 hz 1 60 hz table 20 input switch mode. yc condition 0 cvbs mode 1 yc mode table 21 phase 1 lock indication. sl condition 0 not locked 1 locked table 22 input value i/o port. ip condition 0 low 1 high table 23 standard read-out. sak sbk frq standard 0 0 0 pal second crystal 0 0 1 pal reference crystal 0 1 0 ntsc second crystal 0 1 1 ntsc reference crystal 1 0 0 illegal forced mode 1 0 1 secam reference crystal 11 - colour off
december 1992 15 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 limiting values in accordance with the absolute maximum rating system. (iec134) notes to the limiting values 1. equivalent to discharging a 100 pf capacitor via a 1.5 k w series resistor. 2. equivalent to discharging a 200 pf capacitor via a 0 w series resistor. thermal resistance symbol parameter conditions min. max. unit v cc positive supply voltage - 8.8 v i cc supply current - 60 ma p tot total power dissipation - 530 mw t stg storage temperature - 55 +150 c t amb operating ambient temperature - 10 +65 c esd electrostatic discharge (on all pins) human body model note 1 - 2000 +2000 v machine model note 2 - 200 +200 v symbol parameter thermal resistance r th j-a from junction to ambient in free air 48 k/w
december 1992 16 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 characteristics v cc = 8 v; t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v cc positive supply voltage 7.2 8.0 8.8 v i cc supply current - 45 - ma p tot total power dissipation - 360 - mw input switch y/cvbs input ( pin 26) v 26(p-p) input voltage (peak-to-peak value) top sync - white - 1.0 1.43 v z i input impedance 60 -- k w c input ( pin 25) v 25(p-p) input burst voltage (peak-to-peak value) - 0.3 0.43 v z i input impedance 60 -- k w cvbs output ( pin 22) only address 8a v 22(p-p) output voltage (peak-to-peak value) top sync - white - 1.0 - v z o output impedance -- 500 w v tsl top sync voltage level - 2.8 - v bias generator (pin 8) v 8 digital supply voltage - 5.0 - v subcarrier regeneration g eneral cr catching range note 1 reference crystal 4.4 mhz 400 -- hz reference crystal 3.6 mhz tbf -- hz second crystal 3.6 mhz 300 -- hz j phase shift for 400 hz deviation 4.4 mhz -- 5 deg for 300 hz deviation 3.6 mhz -- 5 deg tc temperature coef?cient of oscillator - tbf - hz/k z i input impedance reference crystal input - 1.0 - k w second crystal input - 1.5 - k w v dep supply voltage dependency - tbf - v f scomb output ( pin 23) v sub(p-p) subcarrier output amplitude (peak-to-peak value) c l = 15 pf 150 200 300 mv v cen comb enable voltage level 4.0 4.2 - v v cdis comb disable voltage level - 0.8 1.4 v
december 1992 17 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 i sink minimum sink current to force output to comb disable level 0.4 - 2.0 ma r gnd value of grounded resistor to force output to comb disable level 0.4 - 2.0 k w acc acc control range - 20 - +5 db change of - (r - y) and - (b - y) signals over acc range -- 1db colour killer threshold pal/ntsc -- 25 - db secam -- 23 - db kill - unkill hysteresis - 3 - db demodulators - (r - y) and - (b - y) outputs (pins 1 and 2) ratio of - (r - y) and - (b - y) signals standard colour bar 1.20 1.27 1.34 tc temperature coef?cient of - (r - y) and - (b - y) amplitude - tbf - hz/k spread of - (r - y) and - (b - y) ratio between standards - 1 - +1 db v 1 output level of - (r - y) during blanking - 2.0 - v v 2 output level of - (b - y) during blanking - 2.0 - v b - 3 db bandwidth - 1 - mhz z o output impedance -- 500 w v dep supply voltage dependency - tbf - v pal/ntsc demodulator v 1(p-p) - (r - y) output voltage (peak-to-peak value) standard colour bar 470 525 585 mv v 2(p-p) - (b - y) output voltage (peak-to-peak value) standard colour bar 595 665 740 mv a crosstalk between - (r - y) and - (b - y) - tbf - db v 1,2(p-p) 8.8 mhz residue (peak-to-peak value) both outputs -- 15 mv v 1,2(p-p) 7.2 mhz residue (peak-to-peak value) both outputs -- 20 mv pal demodulator v r(p-p) h/2 ripple (peak-to-peak value) -- 50 mv s/n signal-to-noise ratio 46 -- db ntsc demodulator j hue phase shift - 45 - deg secam demodulator v 1(p-p) - (r - y) output voltage (peak-to-peak value) standard colour bar 0.94 1.05 1.17 v v 2(p-p) - (b - y) output voltage (peak-to-peak value) standard colour bar 1.19 1.33 1.48 v f os black level offset -- 7 khz s/n signal-to-noise ratio - 43 - db symbol parameter conditions min. typ. max. unit
december 1992 18 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 v res(p-p) 7.8 to 9.4 mhz residue (peak-to-peak value) -- 30 mv f pole pole frequency of de-emphasis 77 85 93 khz ratio of pole and zero frequency - 3 - v cal calibration voltage 345v nl non linearity -- 3% filters t uning v tune tuning voltage 1.5 3.0 6.0 v l uminance delay t d delay time pal/ntsc - 480 - ns secam - 480 - ns b/w - 220 - ns c hrominance trap f o notch frequency f sc = 3.6 mhz 3.53 3.58 3.63 mhz f sc = 4.4 mhz 4.37 4.43 4.49 mhz secam 4.23 4.29 4.35 mhz yc mode; not active b bandwidth at - 3 db f sc = 3.6 mhz - 2.5 - mhz f sc = 4.4 mhz - 3.1 - mhz secam - 3.0 - mhz supp subcarrier suppression 26 -- db c hrominance bandpass f res resonant frequency f sc = 3.6 mhz - 3.58 - mhz f sc = 4.4 mhz - 4.43 - mhz b bandwidth at - 3 db f sc = 3.6 mhz - 1.4 - mhz f sc = 4.4 mhz - 1.7 - mhz c loche filter f res resonant frequency secam 4.26 4.29 4.31 mhz b bandwidth at - 3 db secam 241 268 295 khz sync input v ideo input v 26 sync pulse amplitude y/cvbs input 50 300 600 mv slicing level - 50 - % symbol parameter conditions min. typ. max. unit
december 1992 19 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 t d delay of sync pulse due to internal ?lter 0.2 0.3 0.4 m s s/n noise detector threshold level - 20 - db h hysteresis - 3 - db t d delay between video signal and internally separated vertical sync pulse 12 18.5 27 m s horizontal section clp output (opb/clp mode ); h a output (llc/ha mode ) v oh high level output voltage 4.0 5.0 5.5 v v ol low level output voltage i sink = 2 ma - 0.2 0.4 v i sink sink current 2 -- ma i source source current 2 -- ma t w h a pulse width (32 llc pulses) - 4.7 -m s t d delay between middle of horizontal sync pulse and middle of h a note 2 0.3 0.45 0.6 m s t d delay between negative edge llc pulse and positive edge h a pulse c l = 15 pf 10 20 40 ns t w clp pulse width 21 llc pulses - 3.1 -m s t d delay between middle of horizontal sync pulse and start of clp pulse note 2 3.5 3.7 3.9 m s f irst loop d f frequency deviation when not locked -- 1.5 % svrr supply voltage ripple rejection - tbf - v tc temperature coef?cient - tbf - hz/ c f cr catching range 625 -- hz f hr holding range -- 1.4 khz f static phase shift -- 0.1 m s/khz llc output (llc/h a mode ) f o output frequency 432f h 50 hz standard - 6.75 - mhz 432f h 60 hz standard - 6.80 - mhz v o(p-p) output amplitude (peak-to-peak value) c l = 15 pf 0.25 -- v v o dc output voltage level - 2.5 - v vertical section v ertical oscillator f fr free running frequency forf = 1; divider ratio 628 - 50 - hz forf = 0; divider ratio 528 - 60 - hz f lr frequency locking range 43 - 64 hz symbol parameter conditions min. typ. max. unit
december 1992 20 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 lr divider locking range 488 625 722 v a output v oh high level output voltage 4.0 5.0 5.5 v v ol low level output voltage - 0.2 0.4 v i sink sink current 2 -- ma i source source current 2 -- ma t w v a pulse width 50 hz standard - 160 -m s 60 hz standard - 192 -m s t d delay between start of vertical sync pulse and positive edge of v a pulse - 32 -m s z o output impedance stm = 1 3 -- m w sandcastle output (pin 10) v 10 zero level output voltage 0 0.5 1.0 v i sink sink current 0.5 -- ma h orizontal and vertical blanking v bl blanking voltage level 2.0 2.5 3.0 v i source source current 0.5 -- ma i ext external current required to force the output to the blanking level 1.0 - 3.0 ma t w horizontal blanking pulse width 69 llc pulses - 10.2 -m s t d delay between start of horizontal blanking and start of clamping pulse 45 llc pulses - 6.7 -m s c lamping pulse v clamp clamping voltage level 4.0 4.5 5.0 v i source source current 0.5 -- ma t w pulse width 21 llc pulses - 3.1 -m s t d delay between middle sync of input and start of clamping pulse note 2 3.5 3.7 3.9 m s colour matrix g v gain from r to y - 0.43 - from g to y - 0.84 - from b to y - 0.16 - from r to u out - 0.43 - from g to u out - 0.84 - from b to u out - 1.27 - from r to v out - 1.00 - from g to v out - 0.84 - from b to v out - 0.16 - symbol parameter conditions min. typ. max. unit
december 1992 21 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 output and input/output port o port (opb/clp mode ) v oh high level output voltage 4.0 5.0 5.5 v v ol low level output voltage - 0.2 0.4 v i sink sink current 100 --m a i source source current 100 --m a i/o port (opb/clp mode ) v oh high level output voltage -- v sup v v ol low level output voltage - 0.2 0.4 v i sink sink current 2 -- ma v ih high level input voltage 2.0 -- v v il low level input voltage -- 0.6 v yuv switches (note 3) rgb inputs ( note 3) v i(p-p) input voltage (peak-to-peak value) note 4 - 0.7 1.0 v z i input impedance 3 -- m w uv inputs ( note 3) v i(p-p) u input voltage (peak-to-peak value) note 3 - 1.33 1.90 v v i(p-p) v input voltage (peak-to-peak value) - 1.05 1.50 v z i input impedance (both inputs) 3 -- m w y output v o(p-p) u output voltage (peak-to-peak value) note 4; top sync-to-white - 1.43 - v z o output impedance -- 250 w v o dc output voltage level top sync - 2.5 - v s/n signal-to-noise ratio - tbf - db uv outputs ( note 3) v o(p-p) u output voltage (peak-to-peak value) - 1.33 1.90 v v o(p-p) v output voltage (peak-to-peak value) - 1.05 1.50 v z o output impedance (both outputs) -- 250 w v o dc output voltage level - 2.7 - v g eneral v diff difference between black levels of yuv outputs in rgb mode and yuv mode sync locked -- 10 mv nl non-linearity any input to any output -- 5% b bandwidth any input to any output - 7 - mhz symbol parameter conditions min. typ. max. unit
december 1992 22 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 notes to the characteristics 1. all oscillator specifications are measured with the philips crystal series 4322 143/144. if the spurious response of the reference crystal is less than - 3 db with respect to the fundamental frequency for a damping resistance of 1 k w , oscillation at the fundamental frequency is guaranteed. the spurious response of the second crystal must be less than - 3 db with respect to the fundamental frequency for a damping resistance of 1.5 k w. the catching and detuning range are measured for nominal crystal parameters. these are: load resonance frequency f 0 (c l = 20 pf) = 4.433619 mhz, (second crystal: 3.579545 mhz) motional capacitance c m = 20.6 ff, (second crystal: 14.7 ff) parallel capacitance c 0 = 5.5 pf, (second crystal: 4.5 pf). the actual load capacitance in the application should be c l = 18 pf to account for parasitic capacitances on and off chip. 2. this delay is caused by the low pass filter at the sync separator input. 3. the output signals of the demodulator are called - (r - y) and - (b - y). the colour difference input and output signals of the yuv switch are called uv signals. however, these signals do not have the amplitude correction factor of real uv signals. they are called uv signals and not - (r - y) and - (b - y) to prevent confusion between the colour difference signals of the demodulator and the colour difference signals of the yuv switch. 4. this value refers to signals including a sync pulse. for y signals composed to the rgb inputs this output voltage is 30% lower, as there is no sync pulse on such signals. ct crosstalk between rgb and uv in signals on uv out f = 0 to 5 mhz --- 50 db f ast switch select input ( pin 18) v ih high level input voltage rgb switched on 0.9 - 3.0 v v il low level input voltage uv switched on 0 - 0.5 v g v gain from u in to u out - 1 - from v in to v out - 1 - t d switching delay between pin 18 and yuv -- 20 ns i nput clamp ( pin 17) v ih high level input voltage clamping 2.4 - 5.5 v v il low level input voltage no clamping 0 - 0.6 v t w clamping pulse width 1.8 3.5 -m s v os clamping offset voltage on uv outputs -- 10 mv z i input impedance stm = 1 3 -- m w symbol parameter conditions min. typ. max. unit
december 1992 23 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 quality specification quality level in accordance with urv 4-2-59/601. test and application information notes to figure 8 1. pins 28 and 32 are sensitive to leakage current. 2. the analog and digital ground currents should be completely separated. 3. the decoupling capacitor connected between pins 8 and 9 must be placed as close to the ic as possible. fig.8 application diagram.
december 1992 24 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 package outline unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot232-1 92-11-17 95-02-04 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 29.4 28.5 9.1 8.7 3.2 2.8 0.18 1.778 10.16 10.7 10.2 12.2 10.5 1.6 4.7 0.51 3.8 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 32 1 17 16 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z a max. 12 a min. a max. sdip32: plastic shrink dual in-line package; 32 leads (400 mil) sot232-1
december 1992 25 philips semiconductors product speci?cation pal/ntsc/secam decoder/sync processor TDA9141 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). soldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. repairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.

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